This present invention relates generally to processing within a computing environment, and more particularly to reducing register file ports for register pairs.
Computer architecture data precision is often limited by the hardware. For example, hardware with 64-bit registers will typically be limited to using 64-bit data. In order to extend the precision of the data beyond 64-bits, special processing is required.
One method of extending the precision of data is to use register pairing. Register pairing splits a floating point number, for example, across a pair of hardware registers. By using register pairing the precision of a floating point number can be double what is possible using a single register.
When using register pairing a single operation, such as an add operation, may require the reading of 4 registers and the writing of 2. This requires double the number of read ports to a register file to order to obtain the operands in one access to the registers, or multiple accesses using a single port, which increases operation latency. On a subsequent read of this value the two halves of the operand have to be read out and pieced back together, which further increasing complexity and latency.